1. Field of the Invention
The present invention relates generally to a packet data communication system, and in particular, to an apparatus and method for canceling interference signals at low power in a receiver for a Code Division Multiple Access (CDMA) First Evolution Data and Voice (1x EVDV) communication system, which is a high-speed packet data communication system.
2. Description of the Related Art
Generally, in a CDMA x EVDO communication system, a transmitter uses a quadrature phase shift keying (QPSK) scheme as a modulation scheme for voice signal channels, and transmits signals at a power high enough to overcome a channel error through power control. A receiver combines multipath signals through a rake receiver to increase a signal-to-noise ratio (SNR). However, a high-speed packet data transmission scheme for a CDMA 1x EVDV communication system has evolved into a scheme of adaptively selecting a modulation scheme and a code rate (a ratio of information signals to parity signals) of a channel code according to a channel condition without power control. That is, in the CDMA 1x EVDV communication system, when a mobile station is located close to a base station and has a good channel condition, it transmits signals by using a high-order modulation scheme (e.g., 16-ary quadrature amplitude modulation (16-QAM)) having a high code rate. However, when the mobile station is located far from the base station and has a poor channel condition, it transmits signals by using a low-order modulation scheme (e.g., QPSK) having a low code rate. When the low-order modulation scheme is used, the amount of transmittable information for each frequency band is limited disadvantageously, whereas power of transmission signals advantageously do not need to be high. In contrast, when the high-order modulation scheme is used, the amount of transmittable information for each frequency band is increased advantageously, whereas disadvantageously power of transmission signals must be high. In addition, when the higher-order modulation scheme is used, a signal-to-noise ratio must be higher for satisfactory reception of signals compared to when the existing QPSK modulation scheme is used. For performance improvement of a receiver, it is necessary to remove an interference signal between a unit of chip signals, which was not a big issue in the existing system.
FIG. 1 is a graph illustrating an example of channels used in a CDMA 1x EVDV communication system. The CDMA 1x EVDV communication system employs an adaptive modulation and coding (AMC) scheme and a hybrid automatic retransmission request (HARQ) scheme for high-speed data transmission. There are several possible combinations of modulation schemes, coding schemes and retransmissions, so a packet data control channel (PDCCH) is assigned in addition to a packet data channel (PDCH) in order to transmit information on the possible combinations to a receiver. Referring to FIG. 1, the two channels are time-synchronized with each other and transmitted by the predetermined time (1.25, 2.5, or 5 ms). Therefore, for reception of packet data, a packet data control channel must first be demodulated and channel-decoded to acquire its information, and for this period of time, a packet data signal must be stored in a buffer.
FIG. 2 is a block diagram illustrating an example of a structure of a forward packet data channel (F-PDCH) transmitter in a CDMA 1x EVDV communication system.
An operation of the F-PDCH transmitter will be described in brief with reference to FIG. 2. Data received over the PDCH comprises a packet having a predetermined size. Cyclic redundancy check (CRC) bits are added to the input data packet in a CRC adder 201. An output of the CRC adder 201 is channel-coded (turbo-coded, here) in a tail bit adder 202 and a turbo encoder 203. The purpose of channel coding is to add redundancy to information so that the information becomes robust against an error. The resulting information is larger in size compared with the original information packet. The channel-coded packet is called an “encoded packet.” The encoded packet is channel-interleaved in a channel interleaver 204. The channel interleaving reduces the affect of consecutive errors in terms of time. An output of the channel interleaver 204 is scrambled by an adder 205 and a scrambling pattern generator 206. The scrambling prevents an input signal from having a particular pattern. The scrambled signal is transmitted after being modulated through a subpacket selector 207, a QPSK/8-PSK/16-QAM symbol mapper 208, a symbol demultiplexer (DEMUX) 209, first to Nth Walsh coverers 210, and a Walsh unit of chip signal adder 211.
FIG. 3 is a block diagram illustrating an example of a general packet data receiver in a CDMA 1x EVDV communication system.
An operation of the packet data receiver will be described in brief with reference to FIG. 3. In a finger section 300, a received signal is multiplied by a pseudo-random noise (PN) code and thereafter, the result is multiplied by Walsh codes for corresponding channels to restore modulation symbol information for respective fingers. Outputs of the respective fingers are combined in combiners 301 and 304 in order to combine multipath signals. In a deinterleaver 302 and a Viterbi decoder 303, control information for receiving packet data is calculated from an output of the combiner 301, and for this time period, a packet data signal generated through the combiner 304 and a parallel-to-serial (P/S) converter 305 is stored in a buffer 306. The packet data information stored in the buffer 306 is decoded through a metric generator 307, a deinterleaver 308 and a turbo decoder 309 according to packet data reception control information.
FIG. 4 is a graph illustrating an example of a relationship between a symbol error rate (SER) and a signal-to-noise ratio (SNR) according to modulation schemes. In the graph of FIG. 4, a horizontal axis represents SNR per bit when there is no channel coder. SNR per modulation symbol rather than bit is higher than this.
Referring to FIG. 4, for a fixed symbol error rate, as the modulation scheme has a higher order (i.e., as M is increased), a necessary SNR becomes higher, relatively increasing the influence of an interference signal. That is, when a low-order modulation scheme is used, the influence of an interference signal is disguised by a previous noise signal, so the influence is not significant. However, when a higher-order modulation scheme is used, the influence of a noise signal is relatively decreased, so the influence of the noise signal is relatively significant.
FIG. 5 is a graph illustrating an example of deterioration of a SNR due to multipath signal interference. Specifically, FIG. 5 is a graph illustrating how a signal-to-noise ratio changes when in a dual-path channel model, an interference signal with an amplitude of 1 is applied to one path and an amplitude of an interference signal of the other path is adjusted from 0.1 to 1. In FIG. 5, Ior/Ioc represents a ratio of signals received from a desired base station to signals received from all the other base stations, and SNR refers to a received signal-to-noise ratio for which even an interference signal due to multipath was considered. As illustrated in FIG. 5, when an interference signal from the other base station has a high level (i.e., Ior/Ioc is low), although amplitude of a multipath interference signal is increased, variations in SNR is not so significant. However, when an interference signal from the other base station has a low level, as the amplitude of a multipath interference signal is increased, SNR is converged into a considerably low value.
A scheme for removing such an interference signal is roughly classified into a scheme using a channel equalizer and a scheme using a serial interference canceller (SIC) and a parallel interference canceller (PIC).
FIG. 6 is a block diagram illustrating an example of a general linear channel equalizer used in a receiver for a packet data communication system.
An operation of the linear channel equalizer will be described with reference to FIG. 6. An equalizer finger 601 filters a received signal, and a multiplier 602 multiplies an output of the equalizer filter 601 by a PN code. An accumulator comprised of an adder 603 and a delay 604 periodically accumulates an output of the multiplier 602 to generate an estimation value of a pilot signal, under the assumption that a Walsh code of the pilot signal is 0, i.e., a DC signal. When another code is assigned, the corresponding code is multiplied before being accumulated. A filter coefficient of the equalizer filter 601 is updated according to a difference between the estimation value and an actual value. In a similar manner, the output of the equalizer filter 601 is applied to a multiplier 605 where it is multiplied by a PN code, and an output of the multiplier 605 is applied to a multiplier 606 where it is multiplied by a Walsh code corresponding to the channel. Further, an output of the multiplier 606 is applied to an accumulator comprised of an adder 607 and a delay 608, where it is accumulated at stated periods. Through such a process, an actual estimation value of packet data is calculated.
FIG. 7 is a block diagram illustrating an example of a general parallel interference canceller used in a receiver for a packet data communication system.
An operation of the parallel interference canceller will be described with reference to FIG. 7. A received signal is applied to a rake filter 701 where it is filtered, and an output of the rake filter 701 is applied to a decision block 702 where a provisional decision is made on corresponding data. A PIC 703 generates an estimated interference signal according to the provisional decision value, and subtracts the estimated interference signal from an original signal to thereby remove an interference signal to some extent. When the provisional decision value has no error and an interference signal is compensated with a known channel characteristic, the interference signal can be completely removed at once. However, since the two conditions cannot be simultaneously satisfied, an interference signal is not completely removed at once. An interference signal is completely cancelled through repetition of the above process by a decision block 704, a PIC 709 and a decision block 710.
The above interference cancellers assume that they receive an intact output of an analog-to-digital (A/D) converter, and there is no system designed to provide an effective structure by connecting the interference cancellers to a characteristic of a high-speed packet data channel. A structure for arranging the interference cancellers in a front section of a receiver without considering a characteristic of a high-speed packet data channel has several problems. Among others, the largest problem in a mobile station is that the interference canceller should always operate, thus increasing power consumption of the mobile station. A channel equalizer comprises a large number of multipliers, and a parallel interference canceller also needs a large number of multiplications. Since the high-speed packet data channel is constructed in such a manner that one channel is shared by several users, the number of time slots actually assigned to one mobile station may not be large. However, since the mobile station cannot determine whether desired packet information is carried on a given time slot before receiving the time slot and the interference cancellers are arranged in a front section of the receiver, the interference cancellers must always be turned on, causing a reduction in life span of a battery mounted on the mobile station. For example, in an extreme case, if the conventional interference canceling scheme is used, even though there is no packet being transmitted to a given mobile station, the interference canceller continuously performs unnecessary operations, wasting the battery power of the mobile station.